Asynchronous circuits are not pulsed by a clock signal and function according to a principle of data processing by requests and acknowledgements. Although occurring at the same time as synchronous circuits, they are not developed in the same proportions and today still remain hardly used. However, they have significant advantages, such as clearly lower energy consumption than synchronous circuits, a potential for increased speed in executing calculations, a truly shorter wake-up time (that is, useless to wait for a clock to stabilize) and a recognized resistance to variations in voltage (very useful when the energy supplied to the system is not stable over time). They are subsequently particularly well suited to applications such as WSN-type (Wireless Sensor Network-type) wireless communicating sensor network nodes or the IoT (Internet of Things).
An example of integrating an asynchronous processor, to one or several cores, in a microcontroller for a wireless communicating sensor node is described in the article of Berthier et al, entitled “Power gain estimation of an event-driven wake-up controller dedicated to WSN's microcontroller”, published on pages 1-4 of the Proceedings of the 13th international NEWCAS (“New Circuits and Systems”) conference, which was held in Grenoble (FR) from 7 to 10 Jun. 2015. Although such an asynchronous processor indeed has the advantages mentioned above, it remains sensitive to design, as its execution of interrupt routines is not simple to follow for a programmer. In particular, any debugging action is made difficult. In particular, no on-chip debugging unit is provided.
Yet, in the area of WSN networks or the IoT, the on-chip debugging function is essential to enable a programmer to go and read and write information on all the address space of a microcontroller, to stop the execution of a computer program, or further, to take things one step at a time on an instruction code while this is executed on the microcontroller processor. This function is common in synchronous circuits, but difficult to implement in asynchronous circuits and it is a real obstacle to their development.
An example in asynchronous technology, however, is disclosed in the article of Liang et al, entitled “On-chip debug for an asynchronous Java accelerator”, published on pages 312-315 of the Proceedings of the 6th international PDCAT (“Parallel and Distributed Computing Applications and Technologies”) conference, which was held in Dalian (CN) from 5 to 8 Dec. 2005. It relates to an asynchronous Java accelerator connected to an ICE debugging unit. But in this article, the ICE debugging unit is implemented in synchronous technology and the management as well as the use by the Java accelerator of different signals (D_req, R_req, E_req, M_req, W_req, ICE_req) exchanged with the ICE unit are not clearly described in asynchronous logic, this logic not being further detailed. Moreover, the implementation of debugging functions of the ICE unit is hardware, which brings a certain complexity and a rigidity to the overall architecture.